| 摘要 |
PURPOSE:To reduce the number of output line smaller than the number of word line and to improve the yield and intergration, and to facilitate the layout, by providing the gate circuit which is opened/closed by the selection line between the output line of the decoder and word line of cell array block. CONSTITUTION:Selection lines N0'-N3' are provided almost in parallel direction to the bit line on cell array blocks CA0-CA3, so that the selection of block as well as the selection of the word line WL0-WL3 or WL0'-WL3' is made possible. When the output line WLi is set at H level by word decoder WD, and if the selection line N0 is set at H level, AND gate G0 generates H level output, and word line WL0 is selected; and if the selection line N0' is set at H level, AND gate G0' generates H level output, and word line WL0' is selected. In this way, since 2 word line can be selected by 1 output line, the output line can be reduced to half comparing with the word line.
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