| 摘要 |
PURPOSE:To transfer data efficiently and accurately by transmitting a forced use request signal from a unit where the bus use is the most urgent to inhibit bus request signals from the other units. CONSTITUTION:In case of transmission of the urgent bus request signal, a bus request signal 711 transmitted from the inside of the unit and a bus forced use request signal 271 go to logical '1' together. Output signals 712 and 722 from FFs 301 and 302 go to logical '1' simultaneously with application of a bus common clock 700, and a forced use request signal 6X is outputted to set a forced request signal 60 to logical '0'. An AND gate 303 outputs logical'1' by signals 712 and 722, and a bus request signal 5X is transmitted through an OR gate 306. Thus, bus request signals from units which do not transmit the forced use request signal are inhibited by the signal 60, and the unit which transmits the forced use signal having the highest priority level can use the bus, and the data transfer efficiency is improved. |
