| 摘要 |
The invention relates to a digital data transmission system in which a serial bit stream is converted by means of an n-bit-length shift register into n bit streams with an identical bit rate which are in each case inserted into shift registers by means of a clock obtained from the serial bit stream and divided by n, the shift register contents being checked by means of a decoder for an m-bit-length sync word, and a changeover matrix fed by the shift registers is activated by means of the identified sync word depending on the bit configuration from whose n outputs the bit streams can be removed, and is characterised in that the bit configuration of the output signal of the decoder is stored in a memory at the start of a synchronisation procedure, in that a signal to control the changeover matrix and a blocking circuit is output by the memory, in that a window signal is generated by a synchronous evaluation circuit which, during a current synchronisation procedure in the blocking operation, through-connects only the procedure-initiating decoder signal for further processing to the synchronous evaluation circuit and in that, when a synchronisation procedure is aborted, the window signal is opened so wide that all decoding signals are through-connected for further processing to the synchronous evaluation circuit (Figure 1). <IMAGE>
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