| 摘要 |
PURPOSE:To accelerate by forming in advance an N type channel layer on a semi-insulating GaAs substrate surface, sequentially depositing Ta, Pt, Au as gate metals and an insulating layer thereon, and then lifting off the GaAs layer and the Au-Ge layer to form source and drain. CONSTITUTION:After Si ions are implated to channel layer regions 3, 4 on the surface of a GaAs substrate 1 with a mask 2, the mask 2 is removed. A plasma CVDSiN film 5 is coated on the surface of the substrate 1, implanting atoms are activated, the film 5 is then removed, and a Ta layer 6, a Pt layer 7, an Au layer 8 and an SiO2 film are sequentially deposited. Then, a resist pattern 10 is formed, with the pattern as a mask the SiO2 layer 9 and the Au layer 8 are etched, and then the layers 6, 7 are ion etched to form a gate pattern. Subsequently, an N<+> type GaAs layer is grown on the surface of the substrate 1. Then, an Au-Ge, Ni film 14, an n<+> type GaAs layer 12 are selectively removed on the region 15 except the FET region, and an electric connection is performed by wiring electrode 6 made of Ta, Pt, Au. |
