| 摘要 |
PURPOSE:To improve remarkably the simplicity of a digital signal processor and the flexibility of function by reducing remarkably the circuit scale of a digital signal processor and excluding the pattern constitution of a frame synchronizing signal from the limitation of a feedback shift register. CONSTITUTION:Digital multiplex signals D1'''-D4''' form expected digital multiplex signals at the descrambled reception side. The digital multiplex signals D1''' and D2''' are given to a frame synchronizing detection circuit 33 and the digital multiplex signals D3''' and D4''' are fed respectively to a line quality supervisory signal detecting circuit 34 and an auxiliary signal detecting circuit 35. In normal operating state, the function of the 3rd signal processing means is kept normally by the operation of the frame synchronizing system formed by exclusive OR circuits 26, 27, the frame synchronizing detection circuit 33, the 2nd read control means 32 and the 2nd storage means 31 and expected digital multiplex signals D1'''-D4''' are reproduced. |
