Voltage level compensating interface circuit for inter-logic circuit data transmission system

摘要

An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.