| 摘要 |
PURPOSE:To improve the processing ability of a microprocessor, the using efficiency of a bus and the accessing efficiency of a memory by allowing the microprocessor to acquire a common bus. CONSTITUTION:At the time of access to a common memory 5, the microprocessor outputs an acquisition request of the common bus 13. After acquisition, the microprocessor outputs a memory address to an address bus 10, and at the time of memory writing, outputs writing data to a data bus 9 and a memory control signal for discriminating writing/reading to a signal line 11. To identify processors, the microprocessor outputs processor identifying signals assigned to respective processors to a signal line 12. These signals are set up in FIFO registers 1- 4 synchronized with memory system corresponding to respective processors and the common bus 13 is opened. Then, anither processor is set up to common bus 13 acquirable state. When the inputs set up in the FIFO registers 1-4 are outputted to signal lines 14-17 on the output side, a memory 5 is started and access is started. |
