| 摘要 |
PURPOSE:To apply a kind of register file to both high and low speed applications by operating a read address register such as a register file as a delay flip- flop at a high speed and using the register in the through-mode in case of a low speed in matching with the clock speed. CONSTITUTION:In considering that a control pulse T is logic 1, a value of an input D when a clock pulse CP changes from logic 1 to logic 0 appears at an output Q and a determined Q is held independently of the input D when the clock pulse CP takes other state. On the other hand, when the control pulse T is logic 0, the input D appears at the output Q as it is regardless of the value of the clock pulse CP. In bringing the control pulse T to logic 1 in this way, the mode acts like the delay flip-flop mode and when the control pulse T is brought into logical 0, the flip-flop circuit is operated by the through-mode. |
