| 摘要 |
PURPOSE:To generate an N-bit data string with less number of components by providing log2N-set of switches, an FF, a counter and a comparator of log2N- bit and a variable shift register outputting a desired N-bit. CONSTITUTION:The bit location of a 16-bit data is designated by four switches 23-26, the location is stored in a 4-bit FF31 and given to a 4-bit comparator 38. On the other hand, a 4-bit counter 18 counts sequentially 4-bit information and the counted value is given to said comparator 38. The comparator 38 generates an output to an output line 41 when the 4-bit information from the counter 18 is coincident with the storage information of 4-bit from an FF31. That is, a desired output is obtained to a designated bit location. This output is outputted by the variable length shift register 54 while being delayed by 16-bit. |
