发明名称 WIRE VOLTAGE IMPRESSING CIRCUIT OF CMOS READ ONLY MEMORY
摘要 <p>PURPOSE:To improve the operating speed of a memory by constituting the titled circuit so that a voltage of a power supply is applied as it is without causing a voltage drop at read as conventional circuits thereby quickening the establishment of a potential of an address line. CONSTITUTION:A level of an input terminal 30 is ''L'' at read, then the level of nodes 31, 33 go to ''L'', pMOSTQ37, 42 are turned on, nMOSTQ38, Q43 are turned off, the level of nodes 32, 34 go to a voltage VPP of the 2nd power supply VPP, the pMOSTQ44 is turned off and the nMOSTQ39 is turned on. Since the voltage of the node 32 reaches the voltage VPP(=VDD+VTN), the voltage VDD of the 1st power supply VDD is obtained at an output terminal 35 without being effected by the voltage drop of the threshold voltage VTN of the nMOSTQ39. Thus, the establishment of potential of an address line of an EPROM is quickened at read so as to improve the operating speed of the EPROM.</p>
申请公布号 JPS60247898(A) 申请公布日期 1985.12.07
申请号 JP19840102862 申请日期 1984.05.22
申请人 NIPPON DENKI KK 发明人 TANAKA TOSHIAKI
分类号 G11C16/06;G11C17/00;(IPC1-7):G11C17/00 主分类号 G11C16/06
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