发明名称 DATA TRANSFER DEVICE
摘要 PURPOSE:To attain the quick identification of the transmission information through the 2nd device by transferring the serial data sent from the 1st device to a prescribed bit of a prescribed address in a RAM of the 2nd device for each bit. CONSTITUTION:When the 1-bit transmission information is sent from the 1st device 10, an address generating circuit 210 produces the address of a RAM300 according to the contents of a bit address counter 206 which is specified by the serial timing clocks. While a bit address is produced by a bit address generating circuit 211. The 8-bit data corresponding to the address to be stored is read out of the RAM300 by a strobe signal in the read control signal produced from a timing control circuit 209. Then the data replaced with the serial transmission data through a read modifying write circuit 214 is transferred to the original address of the RAM300 by the strobe signal under generation of a write control signal.
申请公布号 JPS60241150(A) 申请公布日期 1985.11.30
申请号 JP19840098093 申请日期 1984.05.16
申请人 FANUC KK 发明人 IKEDA YOSHIAKI;KUWAZAWA MITSURU
分类号 H04L29/08;G05B19/414;G06F12/04;G06F13/42 主分类号 H04L29/08
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