| 摘要 |
PURPOSE:To simplify constitution and to reduce noises for resulting in malfunction at the time of refreshing by providing limitedly a non-synchronous circuit on a synchronous circuit and by limiting the synchronous circuit for a refresh signal generating part. CONSTITUTION:Even if a refresh requirement signal 1 is inputted to a DFF5 while a procedure only for an access requirement signal 2 is under way, a G input is zero and the DFF5 will not change. When the access requirement signal drops, the G input becomes ''1'', and the refresh requirement appears in a Q. An output is transmitted to a shift register 8 through delay circuits 61-64 and a pulse circuit 7, and parallel refresh signals 12 are sequentially transmitted. By entering the 1st shift pulse and the final shift pulse to a J terminal of a JKFF9 and a K terminal, respectively, the entry of an MPU access signal to an AND gate 1 is inhibited during transmission of the refresh signal 12. The delay circuits 61-64, the pulse circuit 7 and the shift register 8 are completely synchronized. |
