| 摘要 |
PURPOSE:To improve the degree of integration without damaging reliability such as a latch-up by forming a groove deeper than junction depth to a substrate or an impurity diffusion layer kept at the same potential as a well as short-circuiting the substrate kept at the same potential by a conductive layer such as a metallic wiring or the well and the impurity diffusion layer. CONSTITUTION:A groove in depth deeper than junction depth is formed in a source region 204 in an (n) channel MOS transistor, and an n<+> impurity diffusion layer 204 in the source region and a (p) well 202 are short-circuited by a grounding electrode 208. Likewise, the same groove is shaped even in a source region 207 in a (p) channel MOS transistor, and a p<+> impurity diffusion layer 207 in the source region and an n type substrate 201 are short-circuited by a power-supply aluminum wiring 210. Accordingly, an additional region for shaping a well contact and a substrate contact is unnecessitated completely, and well potential and substrate potential can be secured positively by an area required for forming a normal MOS transistor. |
