| 摘要 |
PURPOSE:To use an ICE system whose transfer information is formed in 1-byte as a user's system by providing a logical circuit between a CPU of an in-circuit emulator ICE and an interruption control LSI. CONSTITUTION:The interruption control LSI31 receives a consecutively two interruption response pulses, then the LSI31 outputs continuously 2-byte address information. Further, the CPU30 consists of the ICE system, a 1-byte vector is fetched from the LSI31 at interruption response to attain indirect call with a vector in total 2-byte being the sum of its vector and a vector in the CPU30. The logical circuit 32 provided between the CPU30 and the LSI31 divides an interruption signal from the CPU30 into two and outputs a WAIT signal to the CPU30 at the generation of the first split signal. Thus, the CPU30 fecthes the 2nd address information and the transfer address information at interruption is 1-byte. That is, the ICE system having 1-byte of transfer information is used as the user's system. |
