| 摘要 |
PURPOSE:To realize the highly efficiency use of the bus, by selecting the transfer system for a requested device according to the responding speed of an answer device in a system which uses a common bus in a time shared way. CONSTITUTION:When an interlock signal 8 is sent back to a data effective signal 5 from a device to be requested while a bus control circuit 90, a confirmation signal 6 is supplied to a read data latching cicuit 14 via gates 22, 53 and 54 and in the form of a strobe signal 521. the data 2 on the data signal line is stored as a transfer data given from the device to be requested. In case the signal 8 is not sent back to the signal 5 from the device to be requested, the signal 521 is not set at logic 1 to complete a bus cycle. When the data is transferred to the circuit 90 from the device to be requested to be recognized to be a request to a main circuit, the signal 5 is supplied to the circuit 14 as the signal 521. Then the data 2 on the data signal line is latched as the data given from the device to be requested. |
