发明名称 CIRCUIT AND METHOD FOR RESET AT POWER-ON TIME
摘要 PURPOSE:To prevent breakdown of the operation by discharging the electric charge of a capacitor to only a circuit to be supplied, which is operated by a power source voltage, not to flow out this electric charge to external circuits when the power source voltage is varied. CONSTITUTION:When a power source is turned on at a time t0, power is supplied from an external power supply line 2a through a diode 11, and a potential V2 of an internal power supply line 2b rises quickly. At this time, since a capacitor 6 is charged through a resistance 12 because an n-FET13 is turned off, a potential V8 of a signal line 8 rises slowly from a time t1. When the potential V8 exceeds the threshold of an inverter consisting of n-FETs 15 and 17 at a time t3, a terminal 18 goes to the low level to terminate reset, and the circuit to be supplied is set to the operation state. If an accident or the like occurs in a power supply circuit connected to a terminal 1 at a time t4 to cause momentary reduction of the power source voltage and the potential difference between V2 and V8 reaches a threshold VTH of the n-FET13 at a time t5, the n-FET13 is turned on, and the electric charge of the capacitor 6 is discharged to the circuit to be supplied through the internal power supply line 2b. Therefore, reduction of the potential V2 is held down as shown by a solid line in the figure.
申请公布号 JPS60206319(A) 申请公布日期 1985.10.17
申请号 JP19840062784 申请日期 1984.03.30
申请人 TOSHIBA KK 发明人 MATSUMOTO NOBU;WASHIMI MASAHIKO
分类号 H03K17/22 主分类号 H03K17/22
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