| 摘要 |
PURPOSE:To simplify the constitution of an address information generating circuit by triggering the counters of a prescribed notation respectively which are connected in series and producing the address information on directions X, Y and Z respectively. CONSTITUTION:A write control signal (a), a clock (b) or a read control signal (c) and the clock (b) are supplied to a counter circuit 12 consisting of three counters 12a-12c which are connected in series with notation numbers switched by a control circuit respectively from the circuit 4 of a microcomputer, etc. In a write mode, the counter 12a produces an X address of a sub-buffer memory 10 which stores the 1-block information given from a large capacity memory in directions X, Y and Z. The carry signals of the counter 12a are counted by the counter 12b, and a Y address of the memory 10 is produced. In the same way, a Z address of the memory 10 is produced by the counter 12c. In read mode, the counter 12c is triggered and addresses are successively produced in the same way by the counters 12a and 12b. Thus it is possible to obtain an address signal generator of a simple constitution including no ROM, etc. for production of addresses. |
