发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To improve the erasing efficiency of an image memory by reading out data specified at its address from the image memory and then reading prescribed data within a period that the same address is specified. CONSTITUTION:Before reading out data from the image memory 3, a CPU2 sets up erasing data in a latch circuit 12 at first and then outputs a control signal IP and sets up an FF19. If a control signal MEM is inputted under said status, timing counter 15 starts to operate and data are read out from the memory 3 in accordance with a reading address and inputted to an output data latch circuit 14. A control signal WT is applied to the memory 3 during a specific period that the same address is specified after reading out data, and erasing data from the latch circuit 12 are written in the memory 3.
申请公布号 JPS60196855(A) 申请公布日期 1985.10.05
申请号 JP19840053291 申请日期 1984.03.19
申请人 CASIO KEISANKI KK 发明人 NISHIO KIYOKAZU;HARUNA YUTAKA
分类号 G06F12/02;G06F12/00;G06T1/60 主分类号 G06F12/02
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