| 摘要 |
PURPOSE:To set control information of a switch matrix at a high speed with a small-sized integrated circuit by setting it in a parallel at every switch train sharing an output circuit. CONSTITUTION:Input signals I1 and I2 are supplied to an input signal terminal 10 of switch elements Sij (j=1 and 2; j=1 and 2), and output signals O1 and O2 are outputted from an output signal terminal 10' of the element Sij. Each element Sij has a shift register (b) for holding control information to specify connection or release of one switch element (a) and an element (a). A switch control status signal 20, a clear signal 30 and a clock signal 40 from a controller 40 are commonly connected at every row. For instance, the signal 20 is connected to an input signal terminal 20 of the element S21, and an output signal 20' of the element S21 is connected to the input signal terminal 20 of the element S11. The signal 30 and 40 are commonly connected to the elements S21 and S11. Thus the controller CT can control the connection or release of the element Sij at a high speed. |
