发明名称 |
ELECTRONIC PACKAGE TESTING CIRCUIT |
摘要 |
PURPOSE:To enable an operation test of a logic circuit by arranging an input terminal to be used only for operation test on an LSI circuit and a circuit which provides an output from the input terminal with a higher impedance of all of the output terminals and bi-directional terminals of the integrated circuit to electrically cut the logic circuit off the LSI circuit. CONSTITUTION:Output terminals 7 and 8 of an integrated circuit 9 are connected to perform an operation test of a combination logic circuit 14 having an input terminal 15 and to be more specific, the operation of an inverter 17, an AND circuit 18 and a NAND circuit 19 is checked. So, the outputs of AND circuits 1 and 2 go to the L level by setting the input terminal 6 of the integrated circuit 9 at the H level. Therefore, as tristate gates 3 and 4 are turned to a high impedance, the output terminal 7 and the bi-directional output terminal 8 also give a high impedance. This electrically cuts the combination logic circuit 14 in an electronic package off the integrated circuit 9 thereby facilitating the operation test of the logic circuit. |
申请公布号 |
JPS60174963(A) |
申请公布日期 |
1985.09.09 |
申请号 |
JP19840030270 |
申请日期 |
1984.02.22 |
申请人 |
HITACHI SEISAKUSHO KK;NIPPON DENSHIN DENWA KOSHA;NIPPON DENKI KK;FUJITSU KK |
发明人 |
TAKI YOSHIHARU;WAKIMURA YOSHIAKI;SAKURAI YOSHIO;URUSHIBARA TETSUO |
分类号 |
G01R31/28;G01R31/316;H01L21/66;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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