| 摘要 |
Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.
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