| 摘要 |
PURPOSE:To execute efficiently the test up to the limit of data transmission/reception without requiring aid of opposite station by providing a delay time variable set circuit and a frequency variable set circuit to decrease the test time of a data communication system. CONSTITUTION:A data inputted in synchronizing with a clock is stored once in an input buffer (INB) 1 comprising 1 bit or two and inputted again in a first in first out (FIFOM) memory 2 in synchronizing with the clock. The number of bits is decided by the test range of the data speed, delay set time and clock set time. The data inputted to the memory 2 is read in the order of input by a request of an output buffer (OUTB) 2 and transmitted from an output buffer 3. The output buffer 3 reads and transmits data by the control of a delay time set circuit (DLC) 4 and a clock set circuit (FQC) 5 and the data transmitted from a communication controller is reflected as a data having the delay time and data speed in matching with the test range and inputted to the communication controller.
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