| 摘要 |
PURPOSE:To decrease the detecting time of an error bit pattern by detecting an error bit of a division remainder data of a syndrome generating circuit at a programmable logic array, a parallel shifter and a priority decision circuit. CONSTITUTION:A programmable logic array PLA circuit 21 to which a remainder data of a (X<c>+1) syndrome generating circuit 20 is inputted and detecting the position of consecutive 0-bit data of a preacirbed number and a parallel shifter 22 inputting the remainder data and obtaining an error bit pattern data with bit shift in response to a shift bit number designation signal are provided, the encode processing for deciding precedence to the output of the circuit 21 is applied, the shift bit number of the shifter 22 is decided and a shift bit number designation is generation by a precedence decision circuit 23. The error bit pattern data of the shifter 22 is inputted to a latch circuit 3, the bit number data of the circuit 23 is inputted to an error position calculation circuit 6 so as to calculate the error position. |
