发明名称 |
DATA PROCESSING SYSTEM |
摘要 |
In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction. |
申请公布号 |
JPS60146358(A) |
申请公布日期 |
1985.08.02 |
申请号 |
JP19840195884 |
申请日期 |
1984.09.20 |
申请人 |
INTERN BUSINESS MACHINES CORP |
发明人 |
MAAKU EDOWAADO DEIIN;DENISU RII MOORAA |
分类号 |
G06F9/46;G06F9/38;G06F11/00;G06F11/07;G06F13/36;G06F15/16;G06F15/177 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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