发明名称 SEMICONDUCTOR ELEMENT ISOLATION STRUCTURE AND MANUFACTURE THEREOF
摘要 PURPOSE:To obtain an isolation structure suitable for the micro fabrication of elements by a method wherein, in forming an element isolation structure in the surface layer part of a semiconductor substrate, the isolation structure is made of a conductive SiO2 film with an underlying region of the same conductivity type as that of the substrate, but of high impurity concentration. CONSTITUTION:An SiO2 film 22 is adhered on the P type Si substrate 21 having an impurity concentration of 1X10<15>/cm<3>, and a layer for preventing parasitic MOS inversion is formed in the surface layer part of the substrate 21 by B11<+> ion implantation through this film, and this ion is made present in the film 22. Next, the film 22 is etch- removed by corresponding to an active region, and a thin gate SiO2 film 25 is adhered on the surface of the exposed substrate 21. Then, a polycrystalline Si gate electrode 27 with the underlying film 25 is formed at the center of the film 25, and the film 25 at the exposed part is removed, and an implanted layer 26 for adjusting the threshold value of an MOS transistor is formed by another B implantation. Besides, the B in the remaining film 22 is diffused, thus generating a P type region 24 having a concentration of 4.8X10<16>/cm<3> under the film 22. Thus, the isolation structure is constructed by the film 22 and the region 24.
申请公布号 JPS60130137(A) 申请公布日期 1985.07.11
申请号 JP19830238652 申请日期 1983.12.17
申请人 TOSHIBA KK 发明人 KONDOU TAKEO;INATSUKI TATSUYA;SATOU HIDEO
分类号 H01L29/78;H01L21/76 主分类号 H01L29/78
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