| 摘要 |
PURPOSE:To increase the response speed and to prevent the generation of a sag in a vertical synchronizing period by producing a sampling pulse synchronously with the rise edge of a synchronizing signal, i.e., the changing point to a pedestal level from a sink chip level and applying the feedback clamp according to the sampling pulse value. CONSTITUTION:A sampling pulse 52a is synchronous with the changing point of the rise edge of a synchronizing signal 50a. A sample and hold circuit 53 detects a pedestal level in all periods including the vertical blanking period of a frame signal 46. A clamp potential generating circuit 54 compares the sampled pedestal level with the reference value Vref1 and applies a difference signal 54a to clamping circuits 33 and 34 respectively to obtain fixed values in pedestal levels of signals 17 and 18 of both through and delay fields. It is enough to set the voltage holding time of the circuit 53 at about 1H since the sampling interval is set at <=1H. This increases the response speed of a loop 45. |
