发明名称
摘要 PURPOSE:To reduce power consumption while preventing misoperation, by performing the clear out operation and the slow leakage operation as the operation of MISFET provided between the word lines and the ground lines through time split and under the current setting. CONSTITUTION:MISFETQ32 is turned on with the high potential of the line address RA signal at standby, the gate voltage Tc of MISFETQ26 and Q27 provided between the word lines and the ground lines is approximately taken as the power supply voltage VDD and it is turned on at the saturation region, enabling to perform clear out quickly. Next, at chip selection, the RA signal is of low potential and MISFETQ37 is turned on at the leading of the RA start signal RAS, and MISFETQ 26 and Q27 flow the slow leakage current biased with the voltage dividing voltage. That is, the clear out operation and the slow leakage operation as the operation of MISFET are timingly splitted under current setting, allowing to reduce the power consumption while preventing misoperation.
申请公布号 JPS6027115(B2) 申请公布日期 1985.06.27
申请号 JP19770124501 申请日期 1977.10.19
申请人 HITACHI LTD 发明人 ARAKI SHUNEI
分类号 G11C11/407;G11C11/409 主分类号 G11C11/407
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