| 摘要 |
PURPOSE:To realize a high-speed insulating gate transistor having larger punch-through voltage by a method wherein a semiconductor epitaxial layer is provided in such a way as to have an impurity concentration distribution, wherein the concentration reduces gradually, and a source region and a drain region, and in addition to these, a gate electrode, are provided in the structure of the transistor. CONSTITUTION:A p type silicon (Si) is used as a material for a substrate 1 and a p type Si epitaxial layer 41 is deposited thereon. The specific resistance of the epitaxial layer 41 is set at 0.1-1OMEGAcm at first. With proceeding of the deposition of the epitaxial layer 41, introduction of impurities is reduced and the specific resistance of the epitaxial layer 41 is set at 1-20OMEGAcm in the surface. Henceforth, the ordinary process is applied. A gate electrode 8 is provided through a gate insulating film 7, and a source region 5 and a drain region 6 are respectively formed in an n type by performing an ion-implantation in self-alignment using the electrode 8. As this insulating gate transistor uses the epitaxial layer 41 having a superior crystallizability for the use of channel region, the withstand voltage distribution at the gate is excellent and the mobility of carriers, which pass through the channel, can be kept at a higher mobility. Moreover, the spreading of depletion layers in the drain is suppressed by the p<+> type layer in the epitaxial layer 41 and the generation of punch-through is prevented, and moreover, the high-speed operation is not hindered.
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