发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To prevent the use of a bus due to fruitless bus transfer in read modify write RMW operation by displaying the continuation of the RMW operation. CONSTITUTION:When a data processor generates a request to use the bus including the RMW operation and a bus controller accepts the right to use the bus, a signal BSBUSY is held at a level L. Then, a main storage device is informed by a signal BSWRIT that reading operation is in process, and a signal BSRMW signal is held at the level L because of the RMW operation to transfer an address to the main storage device together with a signal BSDVLD. The main storage device holds a signal BSACEP signal at the level L to respond to the signal BSDVLD and also holds a signal BSLOCK to indicate that the RMW operation is carried out. Consequently, the use of the bus due to fruitless bus transfer in the RMW operation is prevented.
申请公布号 JPS6097456(A) 申请公布日期 1985.05.31
申请号 JP19830204724 申请日期 1983.11.02
申请人 NIPPON DENKI KK 发明人 ONODERA YUTAKA
分类号 G06F12/00;G06F9/52;G06F13/16;G06F13/18;G06F15/16;G06F15/177 主分类号 G06F12/00
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