| 摘要 |
PURPOSE:To eliminate the need for usual monitor of an interface and to reduce the load of a CPU by reporting a change of the interface signal state if occurs to the CPU. CONSTITUTION:The 1st latch part 10 delivers an input signal of plural bits as it is when a gate signal is impressed is provided to an interface circuit together with the 2nd latch part 11 which delivers the input signal when a clock signal is impressed and a comparator 13 which compares the input signal of the part 11 with an output signal. When at least one bit of the input signal has a change, the comparator 13 detects this change and delivers an interruption signal. With output of this interruption signal, an input signal is delivered to a data bus via a driver 12. |
