| 摘要 |
PURPOSE:To enable high speed processing of a nonsynchronizing signal in an information processing device by detecting a logical drop in external signals at the lapse of a constant time after an external device raises answer signals and by dropping the answer signals logically. CONSTITUTION:Before the lapse of time (t), a timer 40 generates an H level signal to an AND gate 35 and an L level signal to an AND gate 42. The signal, which is inputted from a terminal (a), is inputted to an FF31, and this output is inputted to an FF32. The output from the FF32 is inputted to an AND gate 33 together with the output of the FF31. An answer enabling signal is inputted to the AND gate 33, and its output is inputted to the S side of an R.S.FF36. Inverted outputs of the FF31 and the FF32 are inputted to an AND gate 34, and outputted to a terminal (b) from an AND gate 39 as a service-out signal. Next, the input signal is inputted to the R side of the R.S.FF36 through an inverter 41, the AND gate 42, etc., after the lapse of time (t). In this way, the processing system is obtained which will not operate erroneously, even if an information signal drops instantaneously due to noise. |
