| 摘要 |
PURPOSE:To simplify the circuit configuration of the titled circuit to simplify an encoding method by providing 1st-4th power series calculating circuits, a multiplying circuit which performs multiplication of the output of the power series calculating circuits, and an adding circuit which inputs the output of the multiplying circuit. CONSTITUTION:By supplying (n) pieces of word signals W0, W1...Wn-1 constituting the unit block of digital data signals to the 1st-4th power series calculating circuits PSOP1-PSOP4, the 1st-4th outputs I(alpha)-I(alpha<4>) are obtained from an expression I by using the alpha as a primitive element. The outputs I(alpha)-I(alpha<4>) are supplied to the multiplying circuits M13-M16, M23-M26, M33-M36, and M43- M46 of alpha<x>, each group being composed of four pieces of circuits, and each output of the multiplying circuits is supplied to exclusive OR circuits ER1-ER16 acting as 16 pieces of adding circuits from a latch circuit. Then the 1st-4th parities alpha<m0>-alpha<m3> are found from the expression II. Thus the parity of the two- error Reed Solomon code is calculated with a simple circuit. |
