SAMPLING CLOCK REGENERATING CIRCUIT

摘要

PURPOSE:To receive a picture accurately by detecting an output level of a difference detecting means by means of a level detecting means when the level exceeds a prescribed range and controlling a voltage controlled oscillator in such a way that a center frequency of a sampling clock is obtained. CONSTITUTION:While a level detection circuit 8 outputs a digital value corresponding to an output value of an integration circuit 7 when the output value is in a range giving a data oscillating a frequency not overflowing nor underflowing a counter 11 to a D/A converter 9, the circuit 8 outputs all 0 so as to zero the output voltage of the D/A converter 9 when the said output value reaches a large value overflowing or underflowing the counter 11, and brings the oscillated frequency of a voltage controlled oscillator VCXO10 to a frequency 8.949MHz being the same frequency as the sampling clock so as to conrol forcibly the VCXO10, allowing to make the count value of the counter 11 during one picture frame to a value F4272.