发明名称 DELAY LINE
摘要 A delay line circuit provides variable delay and phase shift to electric signals propagating along the delay circuit. The circuit is formed of a set of varactors constructed either as varactor chips or as a set of mesas upstanding from a gallium arsenide substrate. A ground plane interconnects bottom terminals of the varactor chips while a strip line conductor interconnects top terminals of the varactor chips. In the case of the mesa configuration, a metallized layer covers the regions between the mesas without contacting the base portions of the mesas. The strip line conductor makes contact with the respective mesas via a set of metallic posts upstanding from respective ones of the mesas. Dielectric material may be inserted between the strip line conductor and the metallic layer to position the strip line conductor relative to the metallic layer, which layer serves as a ground plane in a transmission line comprising the strip line conductor.
申请公布号 AU3255684(A) 申请公布日期 1985.04.04
申请号 AU19840032556 申请日期 1984.08.30
申请人 HAZELTINE CORP. 发明人 NAME NOT GIVEN
分类号 H01P9/00;H03H11/26 主分类号 H01P9/00
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