| 摘要 |
<p>PURPOSE:To release automatically a stop state of the system timing by counting the lock states of system timing signals and releasing the lock state automatically when said count value reaches a prescribed level. CONSTITUTION:A timing clock signal 2 is delivered, and a timing clock release signal 3 is not delivered within a fixed time. In such a case, an FF13 is not reset and a signal 14 is delivered continuously. At the same time, an FF7 is not set and a signal 8 is not delivered either. A counter 20 is counted up by an output signal 18 of the FF13 and the output signal of an NOR gate 19 which has obtained an AND of a basic clock 1. A signal 21 is delivered when the count value of the counter 20 reaches a prescribed level. The signal 21 is sampled by the clock 1, and an FF22 is set. As a result, a signal 6 is delivered from an AND gate 17 to reset the FF13 and set the FF7 respectively. Thus a system timing signal 16 starts running.</p> |
