| 摘要 |
PURPOSE:To transfer and store block data at a high speed by updating a transfer destination address and a transfer origin address in the direction corresponding to address update information, and transferring and storing the block data to and in the same memory. CONSTITUTION:The transfer origin address, transfer destination address, number of transfer words, and address update mode information from a cache memory 3 as the access origin are fetched in a memory controller 2 through a bus 7, and set in a transfer origin address counter 202, transfer destination address counter 203, and address update mode specifying register 201. The register 201 specifies the count modes of the counters 202 and 203 to read data out of the transfer origin memory, address by address, and then updates the contents of the counters 202 and 203 immediately every time the data is written in the trasfer destination memory area to transfer and store the block data from the transfer origin memory area to and in the transfer destination memory area. |
