PROVING SAFE OPERATION

摘要

To prove safe operations of a conventional computer based system the processing hardware is multiplied in parallel channels and the individual results cross-correlated to determine the correct result. The proposed arrangement aims to achieve a comparable level of safety using a single processor channel operating cyclically by correlating results computed during different operating cycles. The processor is also checked frequently, preferably during each cycle to guard against processor faults. The cyclic redundancy approach is then able to disqualify results arising from common mode interference and spurious errors in the processor inputs.