发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 PURPOSE:To simplify the time monitoring of memory access request registered in a buffer means by rewriting the priority of the memory access request read out from the buffer means to prescribed priority by a differencial operation means. CONSTITUTION:The input constant of the differencial operation means 25 enables a memory access request extracting means 26 to extract plural memory access requests registered in the buffer means 22 from the means 22 in accordance with the priority of these memory access requests. Therefore, the priority is determined so that the whole words in the means 22 are read out in a period shorter than a memory access time (inevitably, the number of words in the means 22 is limited by the memory access time and a clock period). Consequently, the means 26 can mask the reading of the already registered memory access requests having lower priority until the memory access request having the highest priority out of the whole memory access requests registered in the means is outputted.
申请公布号 JPS6031666(A) 申请公布日期 1985.02.18
申请号 JP19830139051 申请日期 1983.07.29
申请人 NIPPON DENKI KK 发明人 HASEGAWA MASAO
分类号 G06F13/362;G06F9/46;G06F9/52;G06F12/00;G06F13/18;G06F15/16;G06F15/177 主分类号 G06F13/362
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