| 摘要 |
PURPOSE:To obtain a synchronism generating circuit which outputs a block synchronizing signal suited to the modulation of a biphase mark, by synthesizing the outputs of both the 1st and 2nd counter circuits which count the auxiliary signals of basic clocks and the basic clocks themselves respectively. CONSTITUTION:A block start signal serves as a pulse signal which shows a period between the start time point of a block of an input data signal and the rise time point of the next earliest basic clock. The 1st counter circuit 22 starts its counting with said block start signal and transmits a pulse output when it counts the 1st cycle of the basic clock. The 2nd counter circuit 23 starts its counting with the block start signal and transmits a pulse output when it counts the 2nd cycle of the basic clock. Both counter circuits 22 and 23 hold a fixed level of output until the next block start signal is supplied. An synthesizing circuit 25 synthesizes the outputs of circuits 22 and 23 and outputs the signals having pulses at the 1.5th and 3rd periods of the basic clock obtained from each block start signal. |
