发明名称 PATTERN GENERATING CIRCUIT
摘要 PURPOSE:To generate an optional pattern with optional length through simple circuit constitution by controlling transmit pattern length from a fast RAM through a slow RAM which indicates the frequency of transmission. CONSTITUTION:The slow RAM3 sends a bit for selecting a pattern of the fast RAM1 by an address indicated by an address counter 4 to a signal line (a), and also sends an indication of the frequency of transmission to the RAM1 through an address counter 2. Then, the RAM1 sends out a specified pattern by as many times as indicated. Consequently, an optional pattern with optional length is generated through the simple circuit constitution.
申请公布号 JPS59224575(A) 申请公布日期 1984.12.17
申请号 JP19830085313 申请日期 1983.05.16
申请人 FUJITSU KK 发明人 FUKUSHI MASANORI
分类号 G01R31/28;G01R31/3183;G01R31/319;G06F11/22 主分类号 G01R31/28
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