发明名称 DATA TABLE SYSTEM OF ROM
摘要 <p>PURPOSE:To shorten a processing time without performing complicate arithmetic by allocating various variable signals to address bit columns of an ROM, and storing digital data determined through the allocation according to combinations of addresses corresponding to constituent addresses. CONSTITUTION:When the number of bits of an address bit line of the ROM used for the data table system of the ROM is p+q, one variable X is allocated to the high-order (p) bits of the address bit column and the other variable Y is allocated to the low-order (q) bits. Further, specific data values corresponding to combinations of respective values of those variables are stored previously in addresses indicated by address signals based upon the allocation combinations of corresponding variable values. When data X=Xn and Y=Yn are inputted, a data value Fnn is read out of an address corresponding to an address signal XnYn as an answer corresponding to the combination of both values Xn and Yn. When X=Xm and Y=Ym are inputted, a corresponding data value Fmm is read out to shorten the processing time.</p>
申请公布号 JPS59220817(A) 申请公布日期 1984.12.12
申请号 JP19830094917 申请日期 1983.05.31
申请人 HANSHIN ELECTRIC KK 发明人 UCHISE YOSHIBUMI
分类号 G06F1/02;G06F1/03;(IPC1-7):G06F1/02 主分类号 G06F1/02
代理机构 代理人
主权项
地址
您可能感兴趣的专利