| 摘要 |
A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits coupled to the respective bus lines, and means for sequentially supplying the bus lines with write data, in which the write data are stored in the latch circuits and transferred to selected memory cells of the respective memory cell groups.
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