发明名称 |
Data selection circuit for performance counter |
摘要 |
In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter ("GPPC") connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.
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申请公布号 |
US7404112(B2) |
申请公布日期 |
2008.07.22 |
申请号 |
US20030635103 |
申请日期 |
2003.08.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
ADKISSON RICHARD W.;JOHNSON TYLER;GOSTIN GARY B. |
分类号 |
G06F11/00;G06F11/34;H02H3/05 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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