| 摘要 |
PURPOSE:To quicken the reading time of a register of a data controller by controlling an output buffer of the data controller so as to be an open drain structure at simultaneous read. CONSTITUTION:In case of simultaneous read of the data controller, a PREAD signal goes to an ''H'', resulting that an NMOS transistor (TR)12 is turned on/off depending the state of a DATA signal. That is, when the DATA signal is at the ''H'', the NMOS TR12 is turned on, and when an ''L'', the TR12 is turned off. On the other hand, in a PMOS TR13, an SREAD signal is at the ''L'' independently of the level of the PREAD signal and the TR13 is turned off at simultaneous reading. Thus, an OUT signal is in either OFF state depending on the content of the register at simultaneous read or ON stat of the NMOS TR12. In this state, the NMOS TR12 only is connected, and in case of the simultaneous read depending on the content of data, the NMOS TR12 is turned on or off and it is equivalent that no PMOSTR11 is provded.
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