发明名称 |
DATA STORAGE CIRCUIT OF MICROCOMPUTER |
摘要 |
<p>PURPOSE:To improve the processing speed by extracting directly a data written in a data pointer and transmitting it to an RAM address latch so as to decrease the number of states by one and decrease the instruction cycle. CONSTITUTION:A data written in RAM cells 5-7 being data pointers is fed to an RAM address 2 by address transmission lines 8-10. An RAM address latch 2 latches the data, the data is decoded by a decoder 21 and the information of the RAM cell is outputted to bit lines 14-16 and bit line bars 15-19 by taking the data as an address. A data interface 23 outputs this to an internal bus 3 of the microcomputer. Thus, the states are decreased by one so as to improve the processing speed.</p> |
申请公布号 |
JPS59188760(A) |
申请公布日期 |
1984.10.26 |
申请号 |
JP19830061695 |
申请日期 |
1983.04.08 |
申请人 |
SUWA SEIKOSHA KK |
发明人 |
SATOU HISAO;MIYAYAMA YOSHIYUKI |
分类号 |
G06F15/78;G06F9/34;G06F9/35;G06F12/02;G06F13/00;G11C8/00;G11C11/41 |
主分类号 |
G06F15/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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