| 摘要 |
PURPOSE:To realize a logical circuit where the occupied area is small, the speed is high and the operation is stable, and which is suitable for a decoder output circuit by constituting the 1st MOSFET whose source is connected to the 1st connecting point and the 2nd MOSFET whose source is connected to an output terminal, respectively. CONSTITUTION:The circuit is constituted by the N-chMOSFETQ21 whose source is connected to a connecting point 21, the N-ch MOSFETQ22 whose source is connected to an output terminal OUT, the N-chMOSFETQ23 whose gate and source are connected respectively to the connecting point 22, and the depletion N-chMOSFETQ24 whose drain is connected to the connecting point 22 and whose gate and source are grounded, and which acts like a load element. In setting a gm of the Q23 sufficiently larger than the gm of the Q24, the potential at the connecting point 22 is nearly VDD-VT, and this potential is between the potential of the power supply and a ground potential so that a channel is formed below the gate of an MOS capacitor C23 when the connecting point 21 is at a low potential. |
