发明名称 POLLING CONTROL SYSTEM
摘要 PURPOSE:To design a communication controller with good processing efficiency by adjusting the transmission period of a polling sequence of every terminal device to be fed to communication circuits according to the number of terminal devices connected to the communication circuits, and controlling the device to prevent the overload. CONSTITUTION:A command sent out of a central processor 9 is written at a location displayed as C in a section of an area 141 corresponding to a corresponding communication circuit number (e.g. #1) in a channel-correspondence memory 13. At this time, the address of transmit/receive data in the data buffer 11 of a storage device 10 is written in A and the data length of the transmit/ receive data is written in B. Thus written data in areas 141-14n corresponding to respective communication circuits are read out to a processing register 20 on time-division basis and interruption codes are generated on the basis of the contents and set in a trap register 20, so that the processing is required to a microprogram. Then, even when polling commands are sent out successively, the transmission of polling sequences corresponding to the respective communication circuits is delayed according to the number of terminal devices connected to the communication circuits.
申请公布号 JPS59158150(A) 申请公布日期 1984.09.07
申请号 JP19830032102 申请日期 1983.02.28
申请人 FUJITSU KK 发明人 OKADA TATSUO
分类号 H04L12/403 主分类号 H04L12/403
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