| 摘要 |
PURPOSE:To reduce prasitic capacitance largely by simple structure by arranging a high permittivity porcelain capacitor part to an uppermost layer, a low permittivity porcelain capacitor substrate to an intermediate layer and a bus wiring substrate to a lowermost layer. CONSTITUTION:An annular spacer 13 interposed between a laminated porcelain capacitor part 1 of high permittivity and a low permittivity porcelain capacitor substrate 15 is constituted by a porcelain material of low permittivity such as alumina. An electrode 12 is connected to an electrode 11 for the laminated porcelain capacitor part 1 of high permittivity by an electrode 14 on the spacer 13. An electrode 2 is not in contact with the laminated porcelain capacitor part 1 of high permittivity because the low permittivity porcelain 13 is interposed, and parasitic capacitance is not generated. The capacitor parts 1, 2 and the spacer 13 are bonded firmly with adhesives 16 such as glass while an IC chip 5 is sealed in a closed space surrounded by these three parts. |
