| 摘要 |
PURPOSE:To enable two or four semiconductor integrated circuits to be tested simultaneously reducing the testing time by a method wherein several chips of the same pattern formed on a wafer are arranged so that the sides not yet formed of pad may come into contact with each other every two or four chips. CONSTITUTION:Bonding pads are formed on three sides and the directions of chips are reversed every other row. Resultantly the chips are arranged so that the sides not yet formed of pad of the two adjoining chips c1, c2 may come into contact with each other. At every assembly of two chips (c) on a semiconductor IC wafer substrate, pointers (a) for electric connection are mechanically connected with each other to perform electrical tests of the two chips simultaneously. Any defect such as dispersion of the length of pointers (a) may be corrected remarkably enabling two chips (c) to be tested easily although the sides being able to form the pads (b) are limited to the three sides of chips (c). |
