发明名称 |
Word group redundancy scheme |
摘要 |
A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.
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申请公布号 |
US4462091(A) |
申请公布日期 |
1984.07.24 |
申请号 |
US19820352916 |
申请日期 |
1982.02.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KNEPPER, RONALD W.;LUDLOW, PETER J.;PETROSKY, JR., JOSEPH A. |
分类号 |
G11C11/413;G11C29/00;G11C29/04;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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